From Full-Custom to Gate-Array ASIC for Hardware IP Protection

The employment of fully reconfigurable logic and routing modules represents a promising and potentially resilient approach to combating intellectual property (IP) piracy and the overproduction of integrated circuits (IC). Over time, the utilization of such reconfigurable logic has evolved within the realm of hardware security, encompassing a spectrum of protective measures and security monitoring solutions. This evolution underscores a technological transition within this domain, shifting from full-custom ASICs to gate-array ASICs to enhance robustness. This paper delineates the progression within this field, tracing advancements from rudimentary look-up-table based methods to sophisticated partial reconfigurable ASICs featuring embedded FPGAs (eFPGAs). The investigation critically evaluates the merits and limitations of each technique, and advocates for a strategic trajectory that optimizes efficiency and upholds the promised robustness.