Improving Hardware Security Through Logic-Probability- Guided Gate Replacement Using Emerging Devices

Security threats in the integrated circuit (IC) supply chain are intensifying as demand drives fabrication to off-shore, potentially untrusted foundries. To mitigate theft and reverse engineering, recent work has focused on logic locking, encryption, and camouflaging. This paper introduces a probabilistic logic-driven algorithm that selects optimal locations for polymorphic gate replacement to strengthen circuit protection. Our approach leverages emerging polymorphic devices—namely the Giant Spin-Hall Effect (GSHE) switch, the 5-terminal magnetic domain wall motion (DWM) device, and the threshold-voltage-defined (TVD) switch—to diversify functional behavior and obscure true circuit intent. Evaluated on ISCAS-85 and ISCAS-89 benchmarks under state-of-the-art SAT and AppSAT Attacks, the proposed method substantially increases decryption time while achieving a marked improvement in Output Corruption Rate (OCR) relative to prior techniques. In particular, by deploying the GSHE Switch at the highest-probability nodes, we achieve more than 40% OCR along with strong resilience against SAT and AppSAT Attacks, further demonstrating the effectiveness of the proposed approach as a practical and scalable hardware obfuscation strategy.