A 0.35mm² 94.25μ W Fully Integrated NFC Tag IC Using 0.13μ m CMOS Process

An NFC tag chip employing the ISO/IEC14443-A protocol is developed in SMIC 0.13 <tex-math notation="LaTeX"></tex-math> m EEPROM 2P6M CMOS process, boasting a chip area of 620.03 <tex-math notation="LaTeX"></tex-math> m <tex-math notation="LaTeX">×</tex-math> 567.93 <tex-math notation="LaTeX"></tex-math> m and a power consumption of under 100 <tex-math notation="LaTeX"></tex-math> W. The chip addresses critical issues such as reducing power consumption and minimizing area costs for covering numerous IoT nodes. For a small area of the chip, a specialized ESD protection circuit is proposed, efficiently multiplexing discharge transistors, cross-gate connected rectifiers, limiters for overvoltage protection, and load switch modulators within the chip's limited space. For power efficiency, a compact 175.44 <tex-math notation="LaTeX"></tex-math> m <tex-math notation="LaTeX">×</tex-math> 32.98 <tex-math notation="LaTeX"></tex-math> m 18.52 <tex-math notation="LaTeX"></tex-math> A LDO based on the current mirror and current feedback is presented for the DC supply during the 100% ASK modulation. Additionally, an ASK demodulator and a 13.56MHz <tex-math notation="LaTeX">±</tex-math> kHz clock generator are designed in compact areas of 62.19 <tex-math notation="LaTeX"></tex-math> m <tex-math notation="LaTeX">×</tex-math> 56.06 <tex-math notation="LaTeX"></tex-math> m and 24.76 <tex-math notation="LaTeX"></tex-math> m <tex-math notation="LaTeX">×</tex-math> 13.14 <tex-math notation="LaTeX"></tex-math> m, respectively. These components ensure stable protocol communication with digital circuits and support a 7kb EEPROM, providing a comprehensive solution for NFC-based IoT information collection.