With the increasing performance of semiconductor, yield rate of chip is decreasing. To avoid this issue, chipletization is researched and various heterogeneous integration options, such as vertical and horizontal, are studied. Especially, examination of 3D integration is flourished due to its energy efficiency and performance, Bonding technology and through silicon via, supply electricity to upper chip, are getting traction as an important technology. In order to improve throughput and reliability, we have developed copper plating chemical which can shorten the plating time with avoiding void. We have confirmed performance of developed chemical and measured electrical measurement to understand the mechanism.
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Nagano et al. (2024) studied this question.
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