Design of an Efficient Reverse Carry Propagate Adder for Area Consumption on VLSI

Digital technologies have had a significant impact in the fields of satellite wired and wireless communication, image processing, digital transmission, and adaptive filtering uses in recent years. Better methods and VLSI architectures have been developed as a result of the growing everyday utilization of digital computing to create DSP systems with reduced area difficulty, quicker speeds, and less energy dissipation. The VLSI architecture was created to reduce the total area delay power needs by minimizing the mathematical difficulties of the processes. Therefore, the goal of this study is to construct an effective reverse carry propagation adder for VLSI safety and area efficiency. In electronic circuits, an adder type called a reverse carry-propagate adder (RCPA) is utilized for computations. It is intended to overcome some of the drawbacks of digital signal processing. The carry input signal is more significant than the output carry in the RCP architecture because the carry indication spreads counter-flowing from the most critical lot to the most minor bit. In the face of delay changes, this carry circulation strategy produces greater stability. A rapid pace and area-saving adjustment is achieved at the shift accumulation step. The delay, authority, and power consumption of all three backward carry propagate full-adder cell designs vary. The reverse carry propagate adder is used to reduce the time needed for computation. In general, Xilinx VLSI software was used to carry out this project. The comparison graph of RCPA bits in the area consumption as and delay period as 32 bit d1 has 148 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ m^2</tex> and Delay time as 22.46 ps.