Multi Glass-Wafer Stacked Technology for 3D Heterogeneously-Integrated Scalable 6G Arrays

This article presents the D-band characterization of General Electric's (GE) high-purity fused-silica (HPFS) substrate processing using microstrip ring resonator (MRR) and required passive devices, such as transmission lines (T-Lines) and power divider, it also supports the development of vertical stacking of HPFS substrates to accomplish 3D Heterogeneous-Integration (3D-HI). To alleviate the glass-wafer fabrication cost and complexity by circumventing TGVs, we proposed (a) capacitively-coupled, finite-ground width and (b) 45-degree mitered cut edge-metallization for connecting front-backside ground layers. The measurements of HPFS exhibit relative permittivity (ε <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> ) of 4.45 while loss tangent (tanδ) of 0.0005 at 140GHz. Moreover, the grounded coplanar waveguide (GCPW) and microstrip T-Lines exhibit minimum per unit loss of 0.3dB/mm and 0.2dB/mm, respectively, for D-band. While, a meandered GCPW T-Line exhibits average per unit loss of 0.5dB/mm at 120–150GHz. Additionally, the radiation performance measured by single-antenna and 1x4 antenna array, illustrates maximum gain of 6.5dBi and 11dBi, respectively. Moreover, the single antenna exhibits 90% while 1x4 array shows 85% measured peak efficiencies for D-Band. Lastly, the 2x2 antenna array based on vertically-stacked, edge-metallized, aperture-coupled, stack patch has been simulated with 22% fractional bandwidth and 10dBi gain to define the future directions of the proposed technology.