High-Density 3D-SiP Vertical Interconnect: Structural Design and Process Sensitivity Analysis for Enhanced Electrical Performance

To meet the demands for high-density integration and broadband RF performance in next-generation electronic equipment, this paper investigates the structural design and process sensitivity of vertical interconnects in three-dimensional stacked system-in-package (3D-SiP). Based on quasi-coaxial matching and low-impedance compensation techniques, three typical vertical interconnect structures are designed: the PCB-BGA-SiP microstrip structure achieves S11 better than −15 dB and S21 < 0.3 dB within 2–20 GHz; the lower stripline–BGA–upper microstrip structure achieves S11 better than −27 dB; the lower microstrip–BGA–upper microstrip structure achieves S11 better than −18 dB within 1–23 GHz. Isolation simulation shows that the isolation between adjacent channels exceeds 55 dB within 25 GHz. For process sensitivity evaluation, physical samples of gold wire bonding parameters (length, diameter, number) were fabricated and tested for S11, confirming that the dual-wire topology extends the effective bandwidth to 2–20 GHz (a 54% improvement over single wire), the third-wire marginal gain is only ~5%, and 25 μm diameter offers the best overall performance. For BGA ball radius and pad pitch, parametric sensitivity analysis via Ansys HFSS was performed (not experimentally validated process variation results), identifying the optimal BGA radius as 0.245 mm with an allowable variation of ±0.015 mm, and the pad center-to-center distance should be controlled near 0.8 mm. Based on these findings, process control strategies are proposed: low-loop wire bonding (loop height < 50–80 μm) with statistical process control; substrate warpage controlled through symmetric copper filling, a thick-middle dielectric stack-up, and distributed symmetric cavity layout, combined with eutectic pressure of 1.5 kPa, validated on 10 fabricated substrates with peak warpage consistently < 80 μm, void rate 4.75%, and solder overflow 94%; and BGA soldering using high-precision vision alignment and controlled collapse (20–35%). This work provides a theoretical basis and practical process pathway for transitioning 3D-SiP vertical interconnects from ideal design to mass production.