Experimental evaluation demonstrates scalable wafer-to-wafer hybrid bonding down to 0.36 μm pitch, highlighting dense interconnects with low defectivity.
Hybrid bonding pitch scaling is critical to continue to support higher chip to chip bandwidth at reduced area and power overhead for chip-to-chip signaling. This paper discusses the scalability of hybrid bonding down to 0.36 μm pitch (or over 7.7M connections/mm2) on Intel backend process. We designed and manufactured an electrically testable test chip with 0.64, 0.48 and 0.36 μm pitch, utilizing a dual damascene via-trench fabrication process. The pre-bond metal-dielectric surface polish process was optimized to achieve required surface topography and roughness across the full wafer; metal bond pads needed sub 2 nm of topography control for sub-micron bonding pitch. Wafer-to-wafer bonding showed good dielectric-dielectric and metal-metal joints which was confirmed by the electrical testing results. The bonded wafers also showed <1% voids across the active area of the wafer.
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Talukdar et al. (2024) studied this question.
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