We demonstrate, for the first time, robust 300nm pitch W2W hybrid bonding for advance logic (CFETs, Logic-SRAM stacking) and memory roadmap products (3D-NAND, 3D-DRAM). Advancing the hybrid bonding capability to service these device roadmaps require not only tight pitches but also Cu pattern densities greater than 20% to achieve the required Input/Output (I/O) densities. This requires innovations in materials engineering, device layout and bonding tool performance. By co-optimizing across the hybrid bond module from bond dielectric, metallization, CMP, surface treatments and bond tool capabilities we were able to demonstrate excellent bonding at 300nm pitch at Cu pattern densities as high as 35%. Module robustness was further validated through excellent wafer level yield on large viachain (upto 5Million links).
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Sherwood et al. (2024) studied this question.
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