Evaluation of Burn-in Technique on Gate Oxide Reliability in Commercial SiC MOSFETs

This is the authors' abstract. We don't add key points for this paper.

This work investigates the behavior of threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(Vₜₕ)</tex> , subthreshold swing (SS), and interface state density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(Dᵢₜ)</tex> of commercial SiC planar MOSFETs during the gate oxide burn-in process. The results indicate that prolonged oxide electric field <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(Eₒₓ)</tex> stress can lead to defect generation at or near the SiC/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface, which degrades the reliability of the gate oxide. This study aims to determine the critical stress time for different values of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Eₒₓ</tex> (used for burn-in) to mitigate excessive <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vₜₕ</tex> shift caused by the increase of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dᵢₜ</tex> in SiC MOSFETs. The research approach employed in this paper offers insights for the optimization of burn-in techniques in the industry, with the objective of reducing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vₜₕ</tex> shift and preventing the degradation of the intrinsic lifetime of gate oxide while ensuring efficiency.