Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays

In this work, we provide a detailed characterization and modeling of the physical mechanisms responsible for the vertical loss (VL) of charge in charge trap (CT) 3D NAND flash arrays. The contributions of charge detrapping (DT) and storage charge loss (SCL) are experimentally separated for the first time. By studying the dependence of SCL activation energy on program / erase cycling dose and programmed level, evidence for the key physical mechanisms contributing to it is provided. Finally, a simple yet effective model is devised which allows to accurately reproduce the VL transients, accounting for the contribution of each physical mechanism to the retention loss. Results are a step ahead towards the understanding of CT 3D NAND data retention.