Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND

In this work, we evaluate the scaling limits of inter-word line oxides for 3D NAND Flash devices. We test different oxide stacks by mimicking the stacked architecture using planar capacitors, in combination with Mo electrodes. We conclude that a ~50% reduction in stack height can be obtained by depositing the High-K liner in the cavity hole and reducing the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> thickness to 12 nm, without compromising device reliability.