Interface Engineering of Trench-Ox for Modern DRAM Devices

As DRAM cells are scaled down, performance and reliability have become critical issues. DRAM reliability issues, including static data retention and tRDL, have proven challenging as interface trap density increases through scaling transistor cells. Some ionic charges, such as Chlorine and Hydrogen, are inevitably in-flowed in DRAM cell transistor during Shallow Trench Isolation process (STI), especially in Trench Sidewall Silicon Oxide (Trench-Ox) formation. These ionic charges not only serve as traps but also have negative impact on DRAM structure. In this paper, we propose a novel interface engineering of Trench-Ox layer that improves DRAM performance and reliability by lowering the impurities. In addition, proposed process aims to improve wiggled patterns of STI.