We report a three-stage power amplifier (PA), using 250-nm indium phosphide (InP) heterojunction bipolar transistors (HBTs), that achieves 18.4% peak power-added efficiency (PAE) with 18.8-dBm associated output power ( <tex-math notation="LaTeX">Pₒut</tex-math> ) and 13.8-dB associated power gain at 221.5 GHz. The amplifier has 19.5-dB peak <tex-math notation="LaTeX">S₂1</tex-math> and 212–238-GHz 3-dB bandwidth. The output stage combines the output power of four power transistor cells, each cell being a capacitively degenerated common-base stage with four parallel HBTs, each HBT having 5- <tex-math notation="LaTeX"></tex-math> emitter length. Within each power transistor cell, separate base dc bias resistances for each emitter finger significantly increase the safe operation area (SOA), allowing dc bias at a greater collector current density at any given collector–emitter voltage. The increased SOA improves the amplifier <tex-math notation="LaTeX">Pₒut</tex-math> and power-added efficiency (PAE). The simulated loss of the 4:1 output power combiner is only 1 dB at 230 GHz. To the authors' knowledge, this is the highest published PAE for a transistor amplifier operating above 200 GHz.
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Alizadeh et al. (2024) studied this question.
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