Multichannel Two-Dimensional MoS2 Nanosheet MOSFET for Future Technology Node

This is the authors' abstract. We don't add key points for this paper.

In this work, we explore the 3-D integration of single layer (SL) and bilayer (BL) MoS <tex-math notation="LaTeX">2</tex-math> in stacked gate-all-around (GAA) nanosheet field-effect transistor (NS-FET) using fully calibrated TCAD simulation for the future technology node. Our research primarily focuses on a comparative analysis between multichannel stacked SL-and BL-MoS <tex-math notation="LaTeX">2</tex-math> NS-FETs with various-width Si NS-FETs, which show that BL-MoS <tex-math notation="LaTeX">2</tex-math> NS-FET outperforms its Si NS-FET counterpart for sub-5-nm technology nodes. The results show that the vertical stacking of SL-and BL-MoS <tex-math notation="LaTeX">2</tex-math> NS-FET significantly enhances the switching performance metrics and provides strong immunity against short-channel effects at aggressively scaled technology nodes over 50-nm wide Si NS-FET counterpart. On the other hand, the Schottky barrier (SB)-type contact with MoS <tex-math notation="LaTeX">2</tex-math> NS-FETs is found to have inferior ON-state and OFF-state characteristics compared to doped-type contacts. Moreover, the CMOS inverter based on BL-MoS <tex-math notation="LaTeX">2</tex-math> demonstrates the potential for lower power consumption at iso-frequency and higher operating frequency at iso-power compared to SL-MoS <tex-math notation="LaTeX">2</tex-math> and Si NS-FETs. Our research underscores that MoS <tex-math notation="LaTeX">2</tex-math> with stacked NS-FETs offers a promising solution for advancing technology nodes to 1 nm and beyond.