Wafer-scale 2D MoS2 transistors with self-aligned angstrom gate length and nanometer channel length

As conventional silicon scaling approaches fundamental physical limits, two-dimensional semiconductors offer a promising pathway for continued transistor miniaturization. Here we show an ultra-scaled vertical MoS2 transistor that combines a sub-1 nm gate and a 10 nm channel length, realized through a dual-self-aligned fabrication strategy. In this architecture, the exposed edge of a monolayer graphene at etched sidewalls serves as an atomically thin gate electrode, while the sidewalls also act as self-aligned masks for defining an ultra-short MoS2 channel through oblique-angle deposition. This co-scaling strategy yields an on-state current density of 23 μA/μm and on/off current ratio exceeding 10⁶. Systematic device simulations further elucidate the electrostatic control, effective gate length, and tunneling-limited scaling behavior of this vertical architecture. Beyond individual transistors, we demonstrate wafer-scale arrays and their integration into logic circuits (inverters, NAND, NOR gates), underscoring the scalability and integration potential of this platform. The simultaneous downscaling of gate and channel lengths in 2D transistors is essential for their application in future electronics. Here, the authors report the fabrication of 2D MoS2 transistors with self-aligned sub-1 nm gate length and 10 nm channel length, showing high performance at the wafer scale.