Passing Word Line-Induced Subthreshold Leakage Reduction Using a Partial Insulator in a Buried Channel Array Transistor

As dynamic random access memory (DRAM) technologies continue to be downscaled, the partial isolation type buried channel array transistor (Pi-BCAT) structure has emerged as an innovative solution for the increasing challenges caused by leakage current adjacent to passing word lines (PWLs). This study reveals that the Pi-BCAT reduces leakage currents by 30% when compared to conventional BCAT structures. Our comprehensive simulations demonstrate that Pi-BCAT is resistant to temperature-induced leakage variations, confirming its significance in promoting consistent device performance and power management. The Pi-BCAT structure is predicted to be crucial in the advancement of DRAM reliability and efficiency, hence initiating further advancements in semiconductor technology.