Machine learning methods for voltage contrast yield analysis

In the manufacturing of CMOS devices, the golden standard for determining yield at various stages of production is electrical testing. This allows for the identification of failing devices or early yield failures before proceeding to subsequent steps. However, the failure of electrical tests can occur due to various reasons inherent to the structures of the devices. Additionally, a comprehensive analysis is necessary to ascertain the root cause of the failure mechanism once a device does not pass the electrical tests.