Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits

In this study, we proposed a method that could efficiently and comprehensively evaluate power-performance-area (PPA) characteristics of CMOS processes across multiple technology nodes. According to the International Semiconductors Technology Roadmaps (ITRS), we have designed and implemented a series of benchmark Ring Oscillator (RO) circuits using a full-scale downsizing approach from 180nm half-pitch node to 28nm node. Simultaneously, we conducted simulations, analysis, and layout design for RO circuits based on six low-leakage (LL) processes: 180nm, 130nm, 90nm, 65nm, 40nm, and 28nm processes. Through longitudinal analysis and comparison of the PPA characteristics across these six processes, the process quality can be better understood, and some reliable conclusions can be drawn to guide design metrics. The proposed method and benchmark circuits can be well extended to future advanced technology nodes.