A Fully Configurable Unified FEC Decoder for LDPC, Polar, Turbo, and Convolutional Codes with Row-First Collision-Free Compression

This paper presents the first chip implementation of a quad-mode decoder for LDPC, Polar, Turbo, and convolutional codes.It offers 9 fully configurable parameters accommodating arbitrary parity-check matrices up to the size of 8192×16384.It supports a broad range of wireless communication standards such as LTE, Wifi, WiMAX, WiGig, ITU, 5gNR, SDA-OCT, and proprietary codes.Through a novel Row-First Collision Free compression algorithm, LDPC memory usage is dramatically reduced by 89.4%.Furthermore, hardware-sharing techniques optimize memory requirements by an additional 36.9%.Operating at 93.08MHz in LDPC mode, the chip achieves a throughput of 1.62Gb/s/iteration at 239mW, with a normalized energy efficiency of 17.95fJ/bit/check/iteration.Its flexibility far exceeds state-ofthe-art configurable and single-mode designs, positioning it as a front-runner in multi-mode decoding chips.