Hardware Efficient FPGA Implementation of a Layered QC-LDPC Decoder for Ultra-Reliable Low-Latency Communications

Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W.