τ-Law-Driven Cross-Level Temporal Optimization for Ultra-Scale Electronic-Photonic Integrated Circuits: Modeling and Experimental Validation

The continuous scaling of semiconductor technology is facing increasing physical limitations, making conventional geometry-driven scaling insufficient for future ultra-scale computing systems. Electronic-photonic integrated circuits (EPICs) provide a promising approach to overcome interconnect and bandwidth bottlenecks; however, existing EPIC design methodologies still suffer from fragmented optimization across different abstraction levels. In this work, we propose a τ-Law-driven design methodology based on temporal scaling for ultra-scale electronic-photonic integrated circuits. By introducing the time constant τ as a unified optimization objective, the proposed framework enables coordinated optimization across device, circuit, chip, and system levels. A mathematical formulation is established to integrate electronic interconnect delay, optical propagation delay, and electro-optical/opto-electrical conversion delays into a unified temporal optimization model. A quantitative evaluation methodology based on representative parameters reported in previous EPIC studies is further developed to analyze the effectiveness of τ-oriented optimization. The proposed approach is further validated using a proof-of-concept electronic-photonic link, where different configurations are experimentally compared in terms of end-to-end latency. The quantitative and experimental results show that coordinated reduction in multiple latency contributions can reduce system-level latency compared with conventional independent optimization, providing a potential pathway beyond geometry-driven scaling toward scalable and automated EPIC design for future photonic computing and heterogeneous integration systems.