A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.
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Wen et al. (2024) studied this question.
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