FPGA-Placement via Quantum Annealing

In this work we explore the use of quantum computers in solving the NP-hard placement problem of the Field-Programmable Gate Array (FPGA) implementation phase and introduce a novel approach suited for current quantum hardware sizes. Adiabatic quantum computing (AQC), with its capability to traverse expansive solution spaces, is a good fit for addressing this combinatorial problem with its exponentially large solution space. Instead of solving a single the whole problem at once, we re-formulate the placement problem as a series of so called quadratic unconstrained binary optimization (QUBO) problems which are subsequently solved via AQC. Our novel formulation facilitates a straight-forward integration of design constraints. Moreover, the size of the sub-problems can be conveniently adapted to the available hardware capabilities. Beside the sole proposal of a novel method, we ask whether contemporary quantum hardware is resilient enough to find placements for real-world-sized FPGAs. A numerical evaluation on a D-Wave Advantage 5.4 quantum annealer suggests that the answer is in the affirmative.