Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs

Field-Programmable Gate Arrays (FPGAs) have become integral components in diverse application domains due to their adaptability and reconfigurable capabilities. However, the intricate nature of FPGA programming poses significant challenges in efficiently harnessing their potential. High-Level Synthesis (HLS) has emerged as a promising approach, simplifying FPGA development by automating Register Transfer Level (RTL) code generation from high-level programming models. Yet, existing HLS tools often lack extensibility, hindering optimization and design portability.