We report on the development and performance of a digitally controlled phase delay with a step of 280 femtoseconds and a dynamic range of 230 picoseconds. Details of the device design and the simulations as well as comparisons with laboratory measurements will be discussed. We describe how we have used this ASIC to stabilize a digital clock to a precision of less than one picosecond.
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Dehmeshki et al. (2024) studied this question.
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