D-Band Low-Noise Differential Amplifier in a 40-nm CMOS

In this paper, we present the design and measurement of a D-band five-stage low noise amplifier (LNA) in a 40 nm CMOS. Transformer-based conjugate matching was employed between the stages, except for the input. For the input, a balun was used to match the LNA input impedance to the midpoint between the minimum noise and maximum gain impedances. The fabricated LNA exhibited a peak gain of 21.8 dB at 140 GHz and 3 dB bandwidth of 15.4 GHz. The measured average noise figure was 8.7 dB at 140~150 GHz. The chip size (excluding the pads) was 0.08 mm2, and it consumed 46 mW from a 0.9 V supply voltage.