High-Level Synthesis Method of Lenet5 for FPGA Implementation

This paper introduces a method of implementing Lenet5, the best-known convolutional neural network, on FPGA (field programmable gate arrays) using HLS (high-level synthesis) tools.HDL (hardware description language) and HLS tools are mainly used in the FPGA implementation of Lenet5.HLS is implemented directly from C code to FPGA, so the development period is short, but compared to HDL, there are limits to the optimization that users can do.In this paper, to improve the operation speed of Lenet5, the memory was duplicated, and the for loop statement was unrolled to execute the execution statements within the loop simultaneously and in parallel without repeating them.To loop unroll the for loop statement, we introduce a method of implementing one-dimensional array variables as registers and dividing two-dimensional or more array variables into multiple memories with the same number of loop statement repetitions.In addition, to improve the access speed of some array variables, we introduce a method of designating a 2-port memory that can be accessed twice within one clock period.The method proposed in this paper is actually implemented on an FPGA, and its performance and pros and cons are compared with existing HDL implementations and HLS methods.