Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design

This work systematically demonstrates a novel recovery scheme for metal–ferroelectric–insulator–semiconductor (MFIS) ferroelectric field-effect transistor (FeFET) memory arrays involving device fabrication, memory operation, and circuit integration. For the first time, the timing to initiate recovery to prolong the endurance of FeFETs is studied. A 100-ns fast-unipolar pulsing (FUP) recovery treatment at optimized timing is exhibited, significantly extending endurance cycles by a factor of 10 <tex-math notation="LaTeX">²</tex-math> , together with a nearly zero loss (0.02%) in memory window (MW) per recovery period and a reduced MW fluctuation. An ultralow recovery-induced time loss ratio of 5 <tex-math notation="LaTeX">×</tex-math> 10 <tex-math notation="LaTeX">⁻⁵</tex-math> % is achieved. Based on the developed scheme, we propose a self-tracking recovery circuit design utilizing current-mode memory sensing to monitor the degree of fatigue and automatically trigger the recovery operation.