We present a novel technique for Electrical Rule Checking (ERC) based on formal methods.We define a relational semantics of Integrated Circuits (IC) as a means to model circuits' behavior at transistor-level.We use Z3, a Satisfiability Modulo Theory (SMT) solver, to verify electrical properties on circuits -thanks to the defined semantics.We demonstrate the usability of the approach to detect current leakage due to missing level-shifter on large industrial circuits, and we conduct experiments to study the scalability of the approach.
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Oulkaid et al. (2024) studied this question.
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