Abstract One such problem that is important in designing reliable circuits is soft due to high-energy particle strikes in combinational circuits. Soft errors affect the configuration bits that determine the circuit routing and logic and produce permanent errors. Though soft errors are temporarily natured, the constant repetitive soft errors of configuration or routing bits can cause permanent functional errors, unless addressed. To overcome this challenge, an extensive SER reduction mechanism is introduced in this study. The approach successfully combines Evolutionary-based Failure Probability analysis, logical implementation via AIG, and multi-level hypergraph-based partitioning. Circuit partitioning is performed by the METIS tool, and logical implementation is provided by the ABC tool. This is a continuous improvement of circuit designs to maximize the SER. These techniques are applied to the ISCAS’85 benchmark circuits, and the results demonstrate a significantly smaller average SER decrease of 23.7% compared to previously reported techniques. The proposed approach highlights its robustness in the design of complex architectures with several flexible examples of circuit designs. This is a practical and scalable method in modern integrated circuits to reduce SER and significantly enhance the reliability of the circuits against a soft error.
Ramasamy et al. (Sat,) studied this question.