Development and Analysis of Subsystem Models of Message Queues Transmitted within both a Reconfigurable Computing System and Accessing the System-Shared Memory

The author of the article presents the main methods of implementing message transmission between processes in modern reconfigurable systems. The objective of this scholarly paper is to examine and explore approaches to the administration of interacting processes. In the article are also displayed the exchange between parallel processes in reconfigurable multiprocessor systems, the drawbacks of software implementations of this mechanism. The characteristics, obtained on functional models and made in the VHDL language, show the high performance of the subsystem of message queues transmitted within the reconfigurable computing system and when accessing the shared memory of the system. There is proposed a type of hardware accelerator that performs the functions of process synchronization. The results of modeling are presented. In addition, in this article are considered some of the methods of interprocess communication using the example of named pipes and shared memory. There is an examination of the issues regarding the study of software tools for measuring the performance of interprocess communication channels. The methods of interprocess communication considered in the article have different performance, that was measured using the 1mbench software package. The primary outcomes of the conducted tests are visually represented in the diagrams. Towards the conclusion of the research article, a comparative analysis between channels and shared memory is presented, focusing on two key parameters: bandwidth and latency. In conclusion, there are drawn the main conclusions and provided an outline of the objectives for the further research on this topic.