Recently, reinforcement learning (RL) algorithms have shown remarkable performance in chip placement scenarios. In this paper, we present TimingDTH, the first timing-driven RL method with deep three-head network. TimingDTH effectively utilizes the timing features, learns from scratch without pretraining, and generates timing-optimized chip placement results. A novel timing feature extraction method is employed to achieve timing optimization. Experiment is conducted on the ICCAD-2015 benchmark. Compared with the state-of-the-art timing-driven solver DREAMPlace4.0, our approach improves total negative slack (TNS) by 11.54% and worst negative slack (WNS) by 1.72%, while significantly saving runtime by 42.39%.
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Yuan et al. (2024) studied this question.
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