Static Leakage Failure Analysis and Improvement for Small Size Sram

Static random access memory (SRAM) is widely used in sensing applications and in a wide variety of other ASIC and system chips. In order to obtain the maximum SRAM capacity while further reducing the chip area, SRAM usually uses the minimum size allowed by the corresponding technology node. However, when the process size is reduced, the static leakage current of the SRAM memory unit will increase, which will lead to an increase in the static power consumption of the system or chip. Therefore, it is of great significance to design a small-size SRAM with low leakage power consumption and satisfactory performance. In this paper, based on the SRAM structure with mature technology and mass production, the size of the SRAM is miniaturized by 20% to develop a smaller size of SRAM, and the static leakage of small size SRAM unit is improved by failure analysis and process optimization. As the distance between the polysilicon gates of small size SRAM unit decreases, the static leakage current becomes larger due to the gate oxygen tunneling current caused by too large contact hole and the PN junction reverse bias current caused by poor growth of metal silicide. By reducing the size of the contact hole and optimizing the growth conditions of the metal silicide, the static leakage current of small size SRAM is reduced to less than 70 μA, fully meeting the design requirements of 150 μA.