Optimization of Polysilicon Gate Etching Process in SONOS Memory Fabrication

The etching process of the SONOS structure plays an important role on the storage performance of the memory cell. Lateral etching problem and sidewall angle control are possible problems in the etching process. Lateral etching has a great impact on the gate CD and uniformity. In this study, the bucket-shaped sidewall morphology of the gate resulting from lateral etching was addressed by adjusting the gas composition during the soft-landing step, primarily by removing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cl₂</tex> . Additionally, controlling the gate sidewall vertically was achieved by etching polysilicon and the block oxide above it in separate steps.