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Semi-floating gate (SFG) transistor is a novel dynamic random access memory (DRAM), which uses an embedded tunneling field-effect (TFET) transistor for charging and discharging the semi-floating gate. The charging efficiency is constrained by the relatively small capacitance due to traditional limited coupling area between control gate and semi-floating gate. In this paper, we report a novel method to fabricate 3D semi-floating gate transistor with three-side-around control gate. Poly cut approach is applied to isolate semi-floating gate and offer additional area (∼66%) for coupling control gate. The increasing capacitance could trap more charges and lead to more obvious difference to the transistor threshold voltage (VT). With the same Read 0 current, the Read 1 current is 6.7 times higher than that of traditional semi-floating gate device. This design provides a technical scheme for further boosting semi-floating gate transistor.
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Yang et al. (2024) studied this question.
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