Threshold Voltage Mismatch Dependence of SRAM Yield Window Simulation

Statistical SRAM yield Vt (threshold voltage) window analysis has become a growing concern for the requirement of high integration density of SRAM under process variations [1]. SRAM read and write yield window is dominated by median value and local variation of read and write margin. It is found that SRAM array have read and write yield when read and write margin need larger than 6 read and write local variation [2]. In this paper, we investigate the correlation between SRAM VT MM and read and write margin local variation by H-spice simulation. Through the optimization of SRAM device VT MM, read and write margin local variation can be improvement. Therefore, we can predict the optimized SRAM yield Vth window based on the optimized read and write margin local variation and the Vth mismatch.