A Variation Tolerant Write Assist Read Decoupled 9T SRAM Cell for Low Voltage Application

Driven by the swift expansion of energy-demanding Internet of Things devices, on-chip SRAM is undergoing a significant evolution to attain reduced power usage. This shift ushers in a new era of self-sufficient and energy-efficient technology. This paper proposes a novel 9-transistor Write Assist Read Decoupled (WARD) SRAM bitcell designed to achieve significant reductions in write latency. The design incorporates a low threshold (V TH ) write access transistor and leverages virtual ground (VGND) assist for low voltage operation at 32 nm CMOS technology node. It demonstrates notable improvements in write delay over conventional SRAM bitcells. At an operating voltage of 0.6 V, the WARD 9T cell offers reduced write ’1’ delay and write ’0’ delay by 3.18x/3.09x/2.42x/2.11x and 1.5x/1.475x/1.4x/1.37x/1.12x/1.118x compared to 9T half select free write assist (HFWA)/10T/9T single bitline (SB)/7T single-ended (SE) and 11T/9T HFWA/10T/9T transmission based read decoupled (TRD)/9T SB/7T SE cell SRAM bitcells respectively. Additionally, WARD 9T cell demonstrates a substantial reduction in read delay by 1.56x/1.56x/8.44x compared to 11T/8T positive feedback controlled (PFC)/9T SB SRAM bitcells, respectively. To validate its performance, the WARD 9T SRAM bitcell undergoes evaluation across various supply voltages, process corners at varied temperature ranges, considering the impact of voltage threshold variations on transistor mismatch through Monte Carlo simulations. Various parameters like write margin and write 1 delay are validated against 30 mV sigma variation in threshold voltage for 2k data points at 3 different temperatures. The latter undergoes further evaluation at different process corners. The comparative analysis includes various pre-existing SRAM cells, highlighting the superior performance of the WARD 9T cell.