A Power/Energy-Efficient 8T SRAM With Reduced Minimum Operation Voltage

This paper aims to design a novel 8T SRAM, engineered to meet the requirements of low-power/energy portable devices. The design is evaluated using 7-nm FinFET technology, operating at a near-threshold voltage of 0.5V. The proposed 8T SRAM bit cell integrates several innovative techniques, including the removal of leakage from the decoupled read path, the use of a single reading transistor, power-gating, and p-type transistor stacking within the latch core. These enhancements collectively result in superior performance metrics. The proposed 8T SRAM offers improvements in read-stability/write-ability by 1.86×/2.41×, with 1.37× higher area than conventional 6T. Furthermore, it achieves reductions in read power, write power, and leakage power by at least 9.31%, 6.65%, and 8.95%, respectively, when compared to top-performing SRAM. Additionally, a failure probability analysis is conducted to determine the minimum operation voltage (Vmin) of the proposed SRAM. The analysis reveals that the proposed 8T design successfully decreases Vmin value from 710 mV (in 6T) to 430 mV.