Mapping Model and Heuristics for Accelerating Deep Neural Networks and for Energy-Efficient Networks-on-Chip

As transistor technology advances and miniaturizes, single chips or multiple chips (chiplets) are now able to integrate hundreds to thousands of cores. Networks-on-Chips (NoCs) have become the standard on-chip communication fabric for chip systems, offering advantages over traditional buses in terms of scalability, parallelism, and power efficiency. Due to these properties of NoC, computations and communications of different layers of deep neural networks (DNNs) can be performed efficiently on NoCs. However, traditional mapping strategies may not be suitable for running DNNs due to the different types of communication patterns, such as communication between layers of DNN and one-to-many and many-to-one communications in fully connected layers. Due to varying communication patterns, it is necessary to map computations for different layers of a DNN in a manner that mitigates the communication bottleneck within the NoC. The goal of this work is to accelerate DNNs running on NoCs while minimizing energy consumption by reducing the computation and communication loads on nodes (cores/routers) and links of NoC. We have mathematically modeled the task-resource co-allocation problem that maps neural networks onto NoC-based multicore systems using mixed integer linear programming (MILP). Then we propose a new mapping algorithm called neighbor-aware, and we adapt simulated annealing and genetic algorithms for faster and energy-efficient mapping of DNNs into NoCs. We present results to show the effectiveness of our proposed approaches for accelerating DNNs mapped to NoCs while providing energy-efficient NoCs.