A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for Real Time Applications

Modern CPUs are operating faster than ever because to the quick development of integrated circuits. On hardware, FIFO frequently acts as the buffer for data transmission and reception. In order to transfer data across systems with various time domains quickly and simply, asynchronous FIFOs can solve a variety of clock domain difficulties. However, stable operation of the system requires adjustment of the clock periods. This paper focuses on making the use of two "2 D Flip flop" as synchroniser to avoid the metastability conditions in the design. Universal gates and status flags have been introduced with Gray Code to increase the speed and efficiency of FIFO. It is anticipated that this paper will serve as a resource for IC designers when they are creating interface circuits and helpful in real time applications as it happens on own time and doesn't need scheduling includes emails, company newsletter, chatting on Slack, and Asana and Trello boards. The results have been verified using the software Xilinx Vivado that the proposed asynchronous design is relatively faster, accurate and consumes relatively lesser power while maintaining comparable performance in terms of delays and metastability. The design presented here is for a 16-bytes FIFO memory which can be modified further as per the memory required.