Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources

In recent years, the accessibility of pins has become a focal point for cell design and synthesis research. In this study, we propose a novel approach to improve routability in upper-level routing by eliminating one M1 track during cell synthesis. This creates space for accommodating upper-level routing, leading to improved routability. We achieve consolidated routability of transistor placement by integrating fast track assignment with dynamic programming-based transistor placement. Additionally, we introduce a hybrid routing algorithm that identifies an optimal cell routing territory for each net. This optimal territory facilitates subsequent Steiner Minimum Tree (SMT) solutions for mixed-integer linear programming (MILP) and constrains the routing region of MILP, resulting in accelerated execution. The proposed MILP approach enables concurrent routing planning and pin metal allocation, effectively resolving the chicken-or-egg causality dilemma. Experimental results demonstrate that, when using the routing-friendly synthesized cell library, the routing quality in various designs surpasses that achieved with a handcrafted cell library in ASAP7 PDK. This improvement is evident in metrics such as wirelength, number of vias, and design rule check (DRC) violations.