Chiplet-based designs, also known as multi-die systems, have introduced a new paradigm that enables significant integration and performance enhancement. Interconnections between different dies are crucial to the success of such designs, where escape routing is commonly employed to satisfy the net connection assignments. Traditional escape routing methods, by and large, are either based on integer linear programming (ILP) or rip-up and reroute optimization, which tend to be inefficient for chiplet-based designs due to the high-density single-layer interconnections and the presence of various obstacles. This work presents an efficient obstacle-avoiding escaping routing method specially designed for die-to-die interconnections in chiplet-based designs, called Chiplet-Escape. Chiplet-Escape divides the complex routing process into multiple sequential stages exhibiting Markov property, where each stage’s optimization only depends on the immediate previous stage’s routing configuration. Chiplet-Escape requires all nets to be moved within each stage to ensure that the routing results of all nets at this stage are determined. Thus, the routing solution for the next stage can be accurately evaluated and decided based on the existing routing results of all nets, avoiding frequent rip-up and reroute operations caused by incomplete routing perspectives in traditional sequential routing methods and improving routing efficiency. Experimental results show that Chiplet-Escape can achieve high routability and a significant 88% runtime reduction compared with a state-of-the-art (SOTA) commercial router.
Ji et al. (Thu,) studied this question.