Chip-scale hermetic packaging of Si PIC with high-speed electronics and photonics

A chip-scale PIC packaging approach is presented for high-frequency devices. The PIC is attached with a multilayer ceramic interposer and the active devices are hermetically sealed in between the PIC and the interposer. The ceramic interposer part provides high-bandwidth RF lines and integration of the electronic ICs and passives, whereas the active photonic chips can be mounted on the PIC and a fiber array attached for the optical interface. The co-packaging approach was optimized and demonstrated for 3-µm SOI PIC platform integrated with low-temperature co-fired ceramics (LTCC) interposers.