Interconnect Stress Testing as a Tool for Assessment of Reliability of Modern PCBs

The of miniaturization can be seen in electronics for some time already. The pinout of active components grows enabling them to have additional functions. The trend in usage of System in a Package (SiP) solutions is also evident thus routing of the active and passive elements became also challenging. To overcome this challenge boards with High Density Interconnection (HDI) where not only through hole, but also different kinds of microvias e.g. blind, buried, stacked, staggered via are used. The standard procedure to test reliability of boards and assemblies is very resource-hungry especially in time and money, as the tests have to be carried out in climatic chambers which lasts for weeks, followed by additional destructive testing like cross-sections. On the other hand IST (Interconnect Stress Testing) is a quick test, that enables to have assessment of the used technology especially the quality of the through holes of all types. Although the coupons are destroyed during the test, it is not necessary to test the manufactured circuits. This saves both materials and time. The technology optimizations and the key findings will be presented within the paper.