Testability Considerations for Custom Processing-In-Memory Cores

In this paper, test considerations and challenges for Processing-In-Memory (PIM) cores are presented and discussed. PIM provides the integration of a local Processing Unit (PU) with RAM (Random Access Memory) on a single Integrated Circuit (IC). This approach to digital system implementation provides the ability to alleviate data transfer rate limitations between the PU and RAM by reducing the timing delays between the processor and memory through a reduction in interconnect delays, and delays introduced by intermediate logic, seen in a traditional processor-memory interfacing approach. However, with new circuit and system architectures, along with higher levels of integration requiring the use of lower geometry fabrication processes, comes the need to effectively and efficiently test the circuits and systems. This paper considers different Design for Test (DfT) approaches and available standards to support test and DfT. In this paper, an IEEE (Institute of Electrical and Electronics Engineers) standard 1500 wrapper is developed to allow the PU and memory to be tested both in isolation and when operating as a single PIM core.