Modeling and simulations have played a critical role in the progress of the microelectronics industry. With the scaling and advancements in the transistor architecture, it is necessary to incorporate higher-order effects to correctly model the behavior of the transistor. This increases the simulation time and computational load. In this work, we explore the use of deep neural networks to simulate the electrostatics of a double gate FET across a wide range of channel thicknesses.
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Singh et al. (2024) studied this question.
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