A Novel Low Loss Planar Gate LIGBT With P-type Buried Layer

A novel low loss LIGBT with p-type buried layer (PLB-LIGBT) is proposed. The PLB-LIGBT features an emitter trench as well as a p-type long buried (PLB) layer inserted in the n-drift region. The proposed structure not only reduces the on-state voltage drop (Vceon), but also reduces the turn-off loss (Eoff) without sacrificing the breakdown voltage $(BV)$. Simulation results show that the Vceon is reduced by 9.5% when compared with the LIGBT with carrier stored (CS) layer (CS-LIGBT), PLB-LIGBT exhibits a 9.5% decrease in Vceon, a 59.8% reduction in turn-off time (toff), a 65% decrease in Eoff, and a 16.5% improvement in $BV$.