SPICE modeling of distance-dependent mismatch for competitive ADC/DAC design (Invited Paper)

Many analog circuit types (DAC, ADC, PLL, references, etc.) rely on good capacitance matching. However, silicon experiments have shown that matching of copper-based backend capacitors significantly deteriorates if their spacing exceeds a few microns [1]. We present a method to capture this effect in a conventional SPICE model library and simulation flow. This makes the effect detectable at design time, which is key to developing first-time-right competitive analog circuits. We also demonstrate the value of this modeling approach on two silicon-evaluated DAC-layouts.