Hybrid CMOS Memristor-Based Data Compressor Using Shannon Fano Encoder

Recently, memristors have been widely employed for building logic circuits as they can be easily integrated with the existing CMOS technology, paving the way for Hybrid Memristor CMOS logic circuits, which mainly decreases the power consumption, die area requirements and further delay associated with the logic circuits. In this work, a Shannon-Fano encoder is designed using Hybrid Memristor CMOS logic, which is widely employed for data compression applications. The key blocks viz. Source Encoder, Decoder, and Priority encoder are built and simulated using Knowm memristor by invoking its SPICE model and TSMC 180nm model files into LT SPICE. Further, the proposed design is found to consume low die area as fewer numbers of transistors were used.